1/10 february 2002 stp12nm50 - stp12nm50fp STB12NM50-1 n-channel 500v - 0.30 w - 12a to-220/to-220fp/i 2 pak mdmesh ? power mosfet n typical r ds (on) = 0.30 w n high dv/dt and avalanche capabilities n 100% avalanche tested n low input capacitance and gate charge n low gate input resistance n tight process control and high manufacturing yields description the mdmesh ? is a new revolutionary mosfet tech- nology that associates the multiple drain process with the company's powermesh ? horizontal layout. the resulting product has an outstanding low on-resis- tance, impressively high dv/dt and excellent avalanche characteristics. the adoption of the company's propri- etary strip technique yields overall dynamic perfor- mance that is significantly better than that of similar competition's products. applications the mdmesh ? family is very suitable for increasing power density of high voltage converters allowing sys- tem miniaturization and higher efficiencies. absolute maximum ratings ( ? )pulse width limited by safe operating area type v dss r ds(on) i d stp12nm50/fp 500v <0.35 w 12 a STB12NM50-1 500v <0.35 w 12 a symbol parameter value unit stp(b)12nm50(-1) stp12nm50fp v ds drain-source voltage (v gs =0) 500 v v dgr drain-gate voltage (r gs =20k w ) 500 v v gs gate- source voltage 30 v i d drain current (continuos) at t c =25 c 12 12(*) a i d drain current (continuos) at t c = 100 c 7.5 7.5(*) a i dm ( l ) drain current (pulsed) 48 48(*) a p tot total dissipation at t c =25 c 160 35 w derating factor 0.88 0.28 w/ c dv/dt(1) peak diode recovery voltage slope 15 v/ns v iso insulation winthstand voltage (dc) -- 2500 v t stg storage temperature 65 to 150 c t j max. operating junction temperature 150 c (1)i sd 12a, di/dt 400a/ m s, v dd v (br)dss ,t j t jmax. (*)limited only by maximum temperature allowed to-220 1 2 3 to-220fp 1 2 3 i 2 pak (tabless to-220) i nternal schematic diagram
stp12nm50/fp/STB12NM50-1 2/10 thermal data avalanche characteristics electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic 1. pulsed: pulse duration = 300 m s, duty cycle 1.5 %. 2. c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . to-220 / i 2 pak to-220fp rthj-case thermal resistance junction-case max 0.78 3.57 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 6a e as single pulse avalanche energy (starting t j =25 c, i d =i ar ,v dd =50v) 400 mj symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 m a, v gs =0 500 v i dss zero gate voltage drain current (v gs =0) v ds = max rating 1 m a v ds = max rating, t c = 125 c 10 m a i gss gate-body leakage current (v ds =0) v gs = 30v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds =v gs ,i d = 250 m a 345v r ds(on) static drain-source on resistance v gs = 10v, i d =6a 0.30 0.35 w symbol parameter test conditions min. typ. max. unit g fs (1) forward transconductance v ds >i d(on) xr ds(on)max, i d =6a 5.2 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs =0 1000 pf c oss output capacitance 180 pf c rss reverse transfer capacitance 25 pf c oss eq. (2) equivalent output capacitance v gs =0v,v ds = 0v to 400v 90 pf r g gate input resistance f=1 mhz gate dc bias=0 test signal level=20mv open drain 1.6 w
3/10 stp12nm50/fp/STB12NM50-1 electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 m s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd = 250v, i d =6a r g = 4.7 w v gs = 10v (see test circuit, figure 3) 20 ns t r rise time 10 ns q g total gate charge v dd = 400v, i d = 12a, v gs = 10v 28 nc q gs gate-source charge 8 nc q gd gate-drain charge 15 nc symbol parameter test condit ions min. typ. max. unit t r(voff) off-voltage rise time v dd = 400v, i d =12a, r g =4.7 w, v gs = 10v (see test circuit, figure 5) 19 ns t f fall time 8 ns t c cross-over time 18 ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 12 a i sdm (2) source-drain current (pulsed) 48 a v sd (1) forward on voltage i sd =12a,v gs =0 1.5 v t rr reverse recovery time i sd = 12 a, di/dt = 100a/ m s, v dd = 100v, t j = 150 c (see test circuit, figure 5) 350 ns q rr reverse recovery charge 5.25 m c i rrm reverse recovery current 30 a safe operating area for to-220 / i pak safe operating area for to-220fp
stp12nm50/fp/STB12NM50-1 4/10 static drain-source on resistance output characteristics thermal impedance for to-220 / i pak thermal impedance for to-220fp transfer characteristics transconductance
5/10 stp12nm50/fp/STB12NM50-1 gate charge vs gate-source voltage capacitance variations normalized gatethreshold voltage vstemperature normalized on resistance vs temperature source-drain diode forward characteristics
stp12nm50/fp/STB12NM50-1 6/10 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuits for resistive load
7/10 stp12nm50/fp/STB12NM50-1 dim. mm inch min. typ. max. min. typ. max. a 4.40 4.60 0.173 0.181 c 1.23 1.32 0.048 0.051 d 2.40 2.72 0.094 0.107 d1 1.27 0.050 e 0.49 0.70 0.019 0.027 f 0.61 0.88 0.024 0.034 f1 1.14 1.70 0.044 0.067 f2 1.14 1.70 0.044 0.067 g 4.95 5.15 0.194 0.203 g1 2.4 2.7 0.094 0.106 h2 10.0 10.40 0.393 0.409 l2 16.4 0.645 l4 13.0 14.0 0.511 0.551 l5 2.65 2.95 0.104 0.116 l6 15.25 15.75 0.600 0.620 l7 6.2 6.6 0.244 0.260 l9 3.5 3.93 0.137 0.154 dia. 3.75 3.85 0.147 0.151 l6 a c d e d1 f g l7 l2 dia. f1 l5 l4 h2 l9 f2 g1 to-220 mechanical data p011c
stp12nm50/fp/STB12NM50-1 8/10 dim. mm inch min. typ. max. min. typ. max. a 4.4 4.6 0.173 0.181 b 2.5 2.7 0.098 0.106 d 2.5 2.75 0.098 0.108 e 0.45 0.7 0.017 0.027 f 0.75 1 0.030 0.039 f1 1.15 1.7 0.045 0.067 f2 1.15 1.7 0.045 0.067 g 4.95 5.2 0.195 0.204 g1 2.4 2.7 0.094 0.106 h 10 10.4 0.393 0.409 l2 16 0.630 l3 28.6 30.6 1.126 1.204 l4 9.8 10.6 0.385 0.417 l6 15.9 16.4 0.626 0.645 l7 9 9.3 0.354 0.366 3 3.2 0.118 0.126 l2 a b d e h g l6 ? f l3 g1 123 f2 f1 l7 l4 to-220fp mechanical data
9/10 stp12nm50/fp/STB12NM50-1 dim. mm inch min. typ. max. min. typ. max. a 4.4 4.6 0.173 0.181 a1 2.49 2.69 0.098 0.106 b 0.7 0.93 0.027 0.036 b2 1.14 1.7 0.044 0.067 c 0.45 0.6 0.017 0.023 c2 1.23 1.36 0.048 0.053 d 8.95 9.35 0.352 0.368 e 2.4 2.7 0.094 0.106 e 10 10.4 0.393 0.409 l 13.1 13.6 0.515 0.531 l1 3.48 3.78 0.137 0.149 l2 1.27 1.4 0.050 0.055 l l1 b2 b d e a c2 c a1 l2 e p011p5/e to-262 (i 2 pak) mechanical data
stp12nm50/fp/STB12NM50-1 10/10 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
|
